Multilayer laser trim interconnect method

ABSTRACT

A method for creating electrical interconnects between a semiconductor die and package. In the preferred embodiment, an insulating material is applied over the die and extends to the substrate contact pads, leaving a portion of each contact pad exposed. Holes are then trimmed through the insulating material, exposing at least a portion of each die bond pad. A conductive material is then applied over the die, flowing into the holes, contacting the die bond pads, and extending out to contact at least a portion of each substrate contact pad. In another preferred embodiment, an electrically conductive bump may be formed on each die bond pad, protruding through said non-conductive material and at least partially through said conductive material. The conductive layer is then laser trimmed, forming conductive patches that serve as electrical interconnects between the die and package substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] Not applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] Not applicable.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention generally relates to a method forsemiconductor packaging and assembly, and in particular to a method forcreating improved interconnections between a die and package substrate.Still more particularly, the invention relates to a method for creatinginterconnects with subsequent layers of insulating and conductivematerials.

[0005] 2. Background Information

[0006] Modern-day semiconductor devices, commonly called microchips, or“die,” are fabricated on wafers, and the wafers are then sawn intogrids, separating the individual chips prior to assembly in a package.Chips are fabricated in a variety of sizes, but typically range fromonly a few millimeters to a couple of centimeters or more in width. Eachchip has numerous electrical signals. Processors, for example, may haveseveral hundred signals. Provisions must be made to electrically connecta die to the component with which it is used (typically, otherelectrical devices and connections on a printed circuit board) and alsoto protect the die from damage or other external conditions that couldhinder its operation. Package engineering, or packaging, is the fieldwithin semiconductor engineering that addresses these needs.

[0007] Typically, as a die is designed, a packaging team will assess itslayout and other requirements to determine the ideal packaging solution.A myriad of requirements may exist for a particular device, includingthermal, reliability, moisture, electrical, package size and costrequirements. As semiconductor devices increase in complexity and shrinkin size, packaging them is becoming more and more challenging as agreater numbers of electrical signals and other connections, such asgrounds, have to be routed from increasingly smaller chips. As this “pincount” increases, new methods must be found to electrically connect thedie to the board while continuing to meet increasingly aggressivepackaging needs.

[0008] Referring now to FIG. 1, signals are typically routed from a die10 by a ring of substantially square electrical “bond pads” 12 locatedon the edge of the die surface 14. These miniscule bond pads 12 may beless than five one-hundredths of a millimeter (0.05 mm) wide, and spacedjust slightly farther apart, to account for surrounding circuitry 16.

[0009] Historically, as shown in FIG. 2, chips with a relatively low“pin count,” or number of bond pads, have been packaged using“leadframes” 20, thin etched or stamped metal frames which have acentral area, or flag 22, to which a chip is attached. Referring now toFIG. 3, leadframes 20 generally have metal “fingers” 30, pointing inwardtowards flag 22, which are connected to substantially square electrical“bond pads” 12 around the edge of die 10 with hair-like wires 32, whichmay be 25 thousandths of a millimeter (0.025 mm) or smaller in diameter.This assembly process, called “wirebonding,” is performed by extremelyprecise robotic machines called wirebonders (not shown). FIG. 4 shows afull die 10 wirebonded to a leadframe 20.

[0010] As shown in FIG. 5, once the die 10 has been attached to flag 22by an epoxy 50 or other adhesive and bonded to leadfingers 30 with wires32, the die 10 is then encapsulated, typically with a solid plastic moldcompound 52, or ceramic housing (not shown). Lead fingers 30 then carrythe signals out of the edges of the package 54 by doubling as “feet” 56that are fashioned to contact or pass through specific electrical“lands” (not shown) on the board 58.

[0011] Several issues exist with peripherally leaded packages. Forinstance, as all the signals on the die must be routed out the edge ofthe package, as pin count increases, the footprint of the package may beundesirably forced to increase geometrically since the package area isnot utilized for interconnects. Current leaded packages are typicallyoffered in certain predetermined pin counts (such as 100, 112, or 144leads) with each pin count corresponding to a certain size package(e.g., 10×10, 14×14 or 20×20 mm). For this reason, small increases inthe pin count of the die can cause relatively large increases in overallpackage area, since exceeding the number of pins in one package sizewould force the die into the next larger package family.

[0012] The desire to reduce the size of consumer and other types ofelectronics (e.g., cell phones, laptop computers, etc.) creates pressureon chip manufacturers to reduce the size of semiconductor packages.Further, a myriad of issues exists with wirebonding, the defaultinterconnect method used with leadframe packages. Referring now to FIG.6, in the case of plastic packaging, a solid mold compound (not shown)is often unidirectionally injected into the corner of a mold cavity (notshown) around the wirebonded die 10 and spreads out in a pattern 60. Thesolid mold compound serves to protect the chip and interconnects.

[0013] As the mold compound spreads over die 10, it contacts and pushesagainst wires 32 causing them to bend out or “sweep” a small distance asshown. For this reason, packaging design guidelines limit wire lengthand pitch, or the distance between adjacent wires 32, to preventshorting. For a fine-pitch die, or a die that requires a wire pitchsmaller than current high-volume industry standards, and thus, requiresa special wirebonder and thinner wires 32, the issue of wire sweepbecomes even more troublesome.

[0014] Wire sag is also an issue with relatively long or thin wires,which have an inherent sag under their own weight due to their extremelysmall cross-sections. It is essential that wires do not contact theedges of the die or lead fingers to prevent physical damage. Asatisfactory wirebond 32 is shown in FIG. 7A, whereas FIG. 7B shows adrooping wire 32 coming into close contact with the edges of both thedie 10 at 72 and lead fingers 30 at 74.

[0015] Wirebonding also adds unwanted height to a package 54, since awirebonding tool (not shown) will typically create a bond by forming asmall ball of metal 70 on a bond pad 12 on the edge of die 10, then arca wire 32 up from ball 70, finally stitching it out to a finger 30 onleadframe 20. For small products, such as cell phones or other popularmobile devices, any added semiconductor package height is undesired.

[0016] For these reasons, die with high pin counts or die used in smallelectronics typically utilize area array packages, one of the mostcommon being the ball grid array (BGA) 80, as shown in FIG. 8A, in whichan array of solder balls 82 covers at least part of the bottom surfaceof a thin, multi-layered board, or substrate 84.

[0017] As shown in FIG. 8B, when assembled in a BGA package 80, the die10 is bonded to the central flag 86 of substrate 84, rather than a metalleadframe. Instead of routing signals from the package periphery down tothe board 58 as with a leadframe package, in an area array package, adie 10 may be wirebonded out to conductive “traces” 88 on the substrate84. These individual traces 88 can pass down through the substratelayers using electrically conductive channels, or vias 89, and down tothe bottom layer of the substrate 84, where they are routed to an arrayof solder balls 82, which serve as interconnects to a matching array onthe board 58.

[0018] Packaging using substrates 84 affords considerable routingflexibility, as space may be conserved by overlapping different signaltraces 88 on different layers of the substrate 84. Further, sensitivesignals, which would otherwise interfere with one another if routed outadjacently, may be isolated from one another by surrounding them on thesubstrate bottom with surplus balls 82.

[0019] While area array packaging has met many packaging challenges, thepractice of wirebonding still limits the capabilities and features of apackaged device. More advanced methods of attaching a die to a substratedo exist, such as Controlled Collapse Chip Connection (C4) flip-chippackaging, or simply “flipchip,” a method in which electrical pads onthe top surface of a die are mounted with conductive balls (or “bumped”)then flipped over and bonded top-side-down to similar bumps on thesubstrate surface.

[0020] However, the flipchip process is technically intricate andcomparatively expensive, since the bump array on the substrate surfacemust exactly match that of the die. Also, there is little wiringflexibility, and bumps are difficult to apply to fine-pitch die. Thesecustom, exclusive-use substrates often do not achieve the manufacturingvolumes of more generic packaging means, and consequently can be muchmore expensive. Unlike the exclusive-use substrates used with a flipchipdevice, the present invention could be used with existing die withperipheral bond pads and existing substrates, without need for customsubstrates.

[0021] As chip power and pin counts continue to increase and die sizescontinue to shrink, thermal and electrical concerns increaseconcurrently. Removing heat generated by a die is critical inmaintaining chip performance, and robust interconnects are needed toadequately handle the electrical output of a high-powered chip. As notedabove, it is often desirable to design the smallest die possible.However, occasionally the size and number of bond pads needed forwirebonding around the die edge will force the die to be larger than itotherwise would need to be if, as shown in FIG. 9A, components 90 in thecenter of the die were small enough to leave unused space between themand the ring of bond pads 12. In this case, staggered rows of bond pads12, as shown in FIG. 9B, could be used on a die 10, but this solution isoften avoided due to reduced wire pitches and greater possibility forwire sweep and shorting. Therefore, a packaging interconnect method isneeded that maintains or improves upon the benefits of current packagingtechnology while addressing one or more of the aforementioned issues.

BRIEF SUMMARY OF THE PREFERRED EMBODIMENT OF THE INVENTION

[0022] The problems noted above are solved in large part by a method ofcreating electrical interconnects between a die and package without theuse of wirebonds. Without wirebonds, the problems discussed above areeliminated or at least ameliorated to a great extent. Accordingly, thepreferred method is to electrically connect a die and package substrateby applying an electrically non-conducting material over a die,extending onto the package substrate, and leaving a portion of thesubstrate contact pads exposed. An electrically conductive material isthen applied over the non-conductive layer, coming into electricalcontact with the die preferably by flowing into holes formed in theinsulating layer over the die bond pads or by contacting conductivebumps which are formed on the die bond pads and protrude through theinsulating layer. Portions of the conductive layer are then selectivelyremoved to form conductive patches between electrical points of contacton the die and substrate contact pads, respectively. Further, thepreferred method entails spraying a layer of conductive ink over aninsulating epoxy or polyimide layer, then laser trimming the conductiveink layer to create separate connection traces.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] For a detailed description of the preferred embodiments of theinvention, reference will now be made to the accompanying drawings,wherein:

[0024]FIG. 1 is a top view of a conventional die;

[0025]FIG. 2 is a top view of a conventional leadframe;

[0026]FIG. 3 is a top view of a corner of a conventional die wirebondedto a leadframe;

[0027]FIG. 4 is a top view of a conventional die wirebonded to aleadframe;

[0028]FIG. 5 is a cross-sectional view of a conventional wirebonded dieinside a leadframe package;

[0029]FIG. 6 is a top view of a corner of a conventional wirebonded dieillustrating wire sweep;

[0030]FIG. 7A is a cross-sectional view of a conventional die with along wirebond inside a leadframe package;

[0031]FIG. 7B is a cross-sectional view of conventional die with a longsagging wirebond inside a leadframe package;

[0032]FIG. 8A is a bottom view of a conventional ball grid array (BGA)package;

[0033]FIG. 8B is a cross-sectional view of a conventional wirebonded dieinside a ball grid array (BGA) package;

[0034]FIG. 9A is a top view of a die with a bond pad ring that isrelatively large in comparison to the internal circuitry of the die;

[0035]FIG. 9B is a top view of a die with staggered bond pads;

[0036]FIG. 10A is a cross-section view of a bumped die covered with aninsulating layer in accordance with a preferred embodiment of thepresent invention;

[0037]FIG. 10B is a cross-section view of a bumped die covered withinsulating and conductive layers in accordance with a preferredembodiment of the present invention;

[0038]FIG. 10C is a top view of a die bonded to a substrate withconductive patches in accordance with a preferred embodiment of thepresent invention;

[0039]FIG. 11 is a cross-sectional view of an unbumped die covered withinsulating and conductive layers in accordance with an alternateembodiment;

[0040]FIG. 12A is a top view of substrate traces interconnected withconventional wirebonds;

[0041]FIG. 12B is a top view of substrate traces interconnected withconductive patches in accordance with a preferred embodiment of thepresent invention;

[0042]FIG. 13 is a cross-sectional view of a bumped die with staggeredbond pads in accordance with a preferred embodiment of;

[0043]FIG. 14A is a cross-sectional view of a bumped die stacked on topof another bumped die with each die covered with insulating andconductive layers in accordance with an alternate embodiment of thepresent invention;

[0044]FIG. 14B is a cross-sectional view of conventionally wirebondeddie stacked on top of a bumped die with the bottom die covered withinsulating and conductive layers in accordance with an alternateembodiment of the present invention; and

[0045]FIG. 15 is a cross-sectional view of a bumped die bonded to asubstrate stitch in accordance with a preferred embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Broadly, the preferred embodiments of the present inventionprovide a method for creating interconnects between a semiconductor dieand a package substrate. The preferred methods generally includesapplying a conductive layer over an insulating layer, and then using alaser or other suitable mechanism to remove or otherwise trim awayportions of the conductive layer, thereby forming conductive patches.FIGS. 10A-10C illustrate one preferred embodiment of the presentinvention.

[0047] As shown in FIG. 10A, a die 10 is attached to a package substrate84. One or more bond pads 12 are formed on the upper surface of die 10at or near the periphery of the die. The bond pads 12 are formed of aconductive material in accordance with known techniques and may serve aselectrical points of contact for connecting die 10 to the packagesubstrate. The upper surface of the substrate 84 includes one or morecontact pads 100 formed thereon, generally by exposing an underlyingmetal layer by known assembly techniques. Electrical interconnects arecreated between the die's bond pads 12 and the contact pads 100 of apackage substrate 84 without using conventional wirebonds, and thus,avoiding the problems noted above associated with wirebonds. In apreferred embodiment of the present invention, conductive “bumps” 102,preferably made of metal, are also formed on bond pads 12 on the dieperiphery. The bumps 102 are electrically connected to circuits in thedie and may alternately serve as the electrical points of contact on die10 in accordance with a preferred embodiment of the present invention.

[0048] An insulating layer 104, preferably any suitable non-conductingmaterial which can be applied to the die, such as epoxy or polyimide, isapplied to the top and sides of the die 10. The insulating layer 104 ispreferably formed by spinning or spraying on a material. The insulatinglayer 104 preferably extends from the upper surface of die 10 outward tocontact pads 100 on the substrate 84, exposing at least a portion ofcontact pads 100. The conductive metal bumps 102 preferably are tallenough so that at least a portion of the bumps 102 protrude up andthrough the insulating layer 104.

[0049]FIG. 10B shows the next step in the process of forming aninterconnect in accordance with the preferred embodiment of theinvention. Referring now to FIG. 10B, a layer of conductive ink 106 issprayed or otherwise applied over the insulating layer 104 on die 10 andexposed areas of contact pads 100 on substrate 84. The conductive ink106 preferably is composed of Acheson Electrodag® or other suitableconductive material that meets the thermal, electrical, reliability andother assembly requirements of the particular die that would be decidedin the design conception stage. As noted above, metallic bumps 102protrude at least slightly through insulating layer 104 after it isapplied, coming into electrical contact with the conductive layer 106.

[0050] The next step in the process is illustrated in FIG. 10C, in whichis shown a top view of a portion of die 10 attached to a substrate 84 isshown. The portion of the die 10 shown in FIG. 10C is denoted by thedashed line. The conductive ink 106 is denoted by the shaded patternthat covers the die 10 and extends away from die 10 to contact pads 100.Conductive ink 106 preferably comes into physical contact with andcovers a large portion of each contact pad 100 to be connected. Thesheet of conductive ink 106 is preferably laser scribed to trim awayportions 105 of ink layer 106, leaving patches 108 of conductive ink 106formed between the trimmed-away portions 105. The conductive patches 108connect the die bond pads 12 to corresponding substrate contact pads100. For example, two of the die bond pads 12 are labeled as 12 a and 12b. Their associated substrate contact pads are labeled as 100 a and 100b, respectively. Conductive patch 108 a electrically connects die pondpad 12 a to substrate contact pad 100 a. Similarly, conductive patch 108b electrically connects die pond pad 12 b to substrate contact pad 100b.

[0051] As shown in FIG. 10C, it is also possible with the preferredembodiments of the present invention to trim the conductive layer 106 sothat a grounded die bond pad 13 is connected to a large plane 107 of theconductive layer on the die surface, thus using conductive layer 106 asa large conduit for the heat to travel off the die and down to thesubstrate. Heat buildup, especially on high-powered die, can adverselyaffect die performance. In another embodiment, the conductive materialcontacting a die bond pad 12 may be connected to an insulating layer onthe substrate away from the die, instead of to a substrate contact pad.

[0052] Alternatively, the die 10 may be unbumped, as shown in FIG. 11.Reference numeral 111 is a close-up showing holes 110 which must be cutinto insulating layer 104 down to the die bond pads 12 prior toconductive layer application so that the conductive ink 106 can flowdown into holes 110, thereby contacting die bond pads 12.

[0053] The preferred embodiments of the present invention have manyadvantages over current assembly methods. Since the interconnects of thepreferred embodiments disclosed herein are formed as fixed layers ofconductive material and not flexible wires, when the package is molded,there is no movable interconnect, and as such, the problem of wire sweepis avoided. By eliminating wires, the preferred embodiments alsoeliminate the possibility for wire sag, giving an added level ofpackaging robustness. Further, wire height is no longer a concern, asthe relatively flat insulating and conductive layers eliminate an arcingwire above the die, generally allowing for flatter packages.

[0054] An additional benefit of the preferred embodiments of the presentinvention is its applicability to fine-pitch die. As shown in FIG. 12A,when a typical substrate package is wirebonded in accordance withconventional techniques, a contact pad 100 somewhat larger than theadjoining trace 88 is required, to allow for a “stitch” bond 114 at theend of a wirebond 32. Also, traces 88 must be spaced sufficiently farapart to avoid shorting between wirebonds due to wire sweep. Referringnow to FIG. 12B, in the present invention, since the entire area oftraces 88 exposed to conductive patches 108 serves as the “bond,” thereis no need for a contact pad 100 wider than the adjoining trace 88. Inaddition, because there are no sweepable wires in the preferredembodiments, and thus, no risk for wires shorting, traces 88 can beplaced much more closely together, as shown in FIG. 12B. Thisflexibility is beneficial in designing a smaller die and package.

[0055] Consequently, in addition to lessening many of reliability issuesassociated with the wirebonding process, the preferred embodiment of thepresent invention also raises the possibility for yield improvements duein combination to the more robust physical structure of theinterconnects of the preferred embodiments and to the smaller die andpackage sizes possible. Since die are fabricated on wafers, the smallerthe die, the more die can be fabricated on a single wafer, therebylowering manufacturing costs and raising assembly throughput.

[0056] As die are assembled into semiconductor packages, more robustassembly methods, such as the laser trim interconnect method of thepreferred embodiment, allow for higher overall manufacturing yields,thus making the chipmaking process more profitable. Additionally,smaller packages are often more desirable to electronics companies, asthe board area, or “real estate,” they use inside an electronic deviceis reduced. Smaller boards allow companies to market smaller electronicproducts or to include additional functionality on existing designs.

[0057] In addition to reliability improvements over wirebonding, thepreferred embodiments also provides particular electrical benefits. Theminiscule bonding wires 32 shown in FIG. 12A are replaced withrelatively wide conductive patches 108 shown in FIG. 12B, relativelyflat areas of conductive material slightly wider than a substrate trace88. Due to their larger cross sections, these wider, rectangularinterconnect patches 108 have a lower resistance than bonding wires 32,thereby reducing interconnect delays, and thus, improving electricalperformance. Also due to their width, as noted above, these patches 108also serve as a superior conduit for heat to be removed from the diesurface more efficiently than with a conventional wire.

[0058] In addition to affording tighter and more robust bonding withfine-pitch die, the preferred embodiments of the present invention allowfor space conservation in other ways. Referring back to FIG. 9B, a bondpad ring may be compressed by staggering the pads 12 into two or morerows. Wirebonding staggered bond pads is often very difficult, as thereduced wire pitch and staggered wires increase the chances of a shortor other mechanical failure. However, in an alternate embodiment of thepresent invention, as shown in FIG. 13, allows staggered pads 12 to bebonded out without the concerns of wirebonding.

[0059]FIG. 13 shows a die with an outer ring of low-height bumps 120 andan inner ring of high-height bumps 122. An insulating layer 104 a isfirst sprayed onto die 10, partially covering the low bumps 120 andallowing their tips to protrude through layer 104 a. After a first layerof conductive ink 106 a is sprayed onto die 10, contacting the ring oflow bumps 120, laser trimming is performed to isolate the conductivepatches (not shown) extending from the low bumps 120 to their respectivesubstrate contacts 100.

[0060] The process is then repeated as a second insulating layer 104 bis applied, this time covering the low bumps 120 completely and onlypartially covering the high bumps 122. A second conductive layer 106 bis then applied, contacting the ring of high bumps 122. To complete theprocess, laser trimming is then performed to create conductive patches(not shown) extending from the high bumps 122 to their respectivesubstrate contacts (not shown).

[0061] In some cases, space on a board is at such a premium that it isdesirable to stack die on top of each other in a package, as shown inFIG. 14A. A similar process to that described above may be used to bondout stacked die. After depositing a first conductive layer 106 a over aninsulating layer 104 a on the lower die 10 a, laser scribing isperformed to create patches in conductive layer 106 a. The patches ofconductive material 106 a electrically connect the lower die 10 a to thesubstrate 84. An insulating layer 104 b is then applied over lower die10 a, insulating it from the die 10 b to be placed on top of it.

[0062] An upper die 10 b is attached in place, and an insulating layer104 c is applied over it, followed by a conductive layer 106 b, which isthen trimmed to form patches of conductive material 106 b, electricallyconnecting the upper die 10 b to the substrate 84. Alternately, theupper die 10 b may be wirebonded to the substrate 84, as shown in FIG.14B, while the bottom die 10 a utilizes the laser trim interconnectmethod of the present invention.

[0063] Substrates 84 used with the laser trim interconnect method mayutilize conventional contact pads 100, shown previously in FIG. 12, inwhich an opening exists in a solder mask layer 124 to expose theunderlying metal contact pad 100, which conductive patch 108 wouldcontact, at the end of a substrate trace 88. Alternately, as shown inFIG. 15, a metal stitch 140 could be created on top of the surface ofsubstrate 84, serving as the contact pad for the conductive patch 108 tointerconnect with the substrate trace 88.

[0064] Various manufacturing processes can be utilized to assemblesemiconductors in accordance with the preferred embodiments of thepresent invention. Metal ion coating may be used as a conductive layerin another embodiment of the present invention. Similarly, any suitableinsulating material, such as glass, may be used in addition to epoxy orpolyimide.

[0065] The laser trim interconnect method is a semiconductor packagingmethod that diminishes many of the assembly, performance and reliabilityissues associated with existing interconnect methods while permittingthe possibility of more aggressive assembly options, greater thermal andelectrical performance and space conservation than conventionalwirebonding and permitting a widely applicable interconnect method.

[0066] Numerous variations and modifications will become apparent tothose skilled in the art once the above disclosure is fully appreciated.Special designs of the insulating or conductive materials can haveadditional functions, such as an insulating serving as a dam or guide tocontrol the flow of the conductive material.

What is claimed is:
 1. A method of electrically connecting asemiconductor die to a package substrate, comprising: (a) applying anelectrically non-conductive material covering at least a portion of saiddie and extending onto said substrate to a plurality of contact padsformed on said substrate; and (b) applying an electrically conductivematerial over said non-conductive material and extending from anelectrical point of contact of said die to at least one contact pad onsaid substrate.
 2. A method as claimed in claim 1, wherein theconductive material is separated into a plurality of conductive patchesby laser trimming away portions of the conductive material.
 3. A methodas claimed in claim 1, wherein a hole is trimmed into the non-conductivematerial over and down to the bond pads, exposing at least a portion ofeach bond pad to be connected.
 4. A method as claimed in claim 1,wherein an electrically conductive bump is formed on each said die bondpad, said bump protruding through said non-conductive material and atleast partially through said conductive material.
 5. A method as claimedin claim 1, wherein the insulating layer comprises a non-conductiveepoxy.
 6. A method as claimed in claim 1, wherein the insulating layercomprises a non-conductive polyimide.
 7. A method as claimed in claim 1,wherein the conductive layer comprises conductive ink.
 8. A method asclaimed in claim 1, wherein the conductive layer comprises a metal ioncoating.
 9. A method as claimed in claim 1, wherein (a) includesspinning the non-conductive material onto the die and package substrate.10. A method as claimed in claim 1, wherein (a) includes spraying thenon-conductive material onto the die and package substrate.
 11. A methodas claimed in claim 1, wherein (b) includes spinning the non-conductivematerial onto the die and package substrate.
 12. A method as claimed inclaim 1, wherein (b) includes spraying the non-conductive material ontothe die and package substrate.
 13. A semiconductor device formed by theprocess of: (a) applying an electrically non-conductive materialcovering at least a portion of said die and extending onto saidsubstrate to a plurality of contact pads formed on said substrate; and(b) applying an electrically conductive material over saidnon-conductive material and extending from an electrical point ofcontact of said die to at least one contact pad on said substrate.
 14. Adevice as claimed in claim 13, wherein the conductive material isseparated into a plurality of conductive patches by laser trimming awayportions of the conductive material.
 15. A device as claimed in claim13, wherein a hole is trimmed into the non-conductive material over anddown to the bond pads, exposing at least a portion of each bond pad tobe connected.
 16. A device as claimed in claim 13, wherein anelectrically conductive bump is formed on each said die bond pad, saidbump protruding through said non-conductive material and at leastpartially through said conductive material.
 17. A device as claimed inclaim 13, wherein the insulating layer comprises a non-conductive epoxy.18. A device as claimed in claim 13, wherein the insulating layercomprises a non-conductive polyimide.
 19. A device as claimed in claim13, wherein the conductive layer comprises conductive ink.
 20. A deviceas claimed in claim 13, wherein the conductive layer comprises a metalion coating.
 21. A device as claimed in claim 13, wherein (a) includesspinning the non-conductive material onto the die and package substrate.22. A device as claimed in claim 13, wherein (a) includes spraying thenon-conductive material onto the die and package substrate.
 23. A deviceas claimed in claim 13, wherein (b) includes spinning the non-conductivematerial onto the die and package substrate.
 24. A device as claimed inclaim 13, wherein (b) includes spraying the non-conductive material ontothe die and package substrate.